FIG. 1 is a circuit diagram of a conventional reference voltage circuit.
As shown therein, a start-up circuit 10 for a conventional reference voltage circuit 20 includes: an inverter 11 for inverting a reset signal /RESET; an NMOS transistor 12 the gate of which receives the output from the inverter 11; and an NMOS transistor 13 the drain of which is connected to the source of the NMOS transistor 12, the gate of which is connected to the drain, and the source of which is connected to a ground voltage Vss.
The reference voltage circuit 20 includes: a PMOS transistor 21 the gate and drain of which are commonly connected at the node N20 with the drain of the NMOS transistor 12, the source of the transistor 21 being connected to the voltage Vcc; a PMOS transistor 22, the source of which is connected to Vcc, the gate of which is connected to the gate of the PMOS transistor 21, forming a current mirror with the PMOS transistor 21; an NMOS transistor 23 the drain of which is connected at the node N20 to the drain of the PMOS transistor 21; a resistor 24 connected between the NMOS transistor 23 and the ground voltage in series; and an NMOS transistor 25 forming a current mirror with the NMOS transistor 23, the gate and the drain of the NMOS transistor 25 being connected to the drain of the PMOS transistor 22 and the gate of the NMOS transistor 23.
The operation of the start-up circuit 10 of the conventional reference voltage circuit 20 will now be explained with reference to FIG. 1.
First, when a source voltage is initially applied to the circuit, the reset signal /RESET maintains a low level for an initial interval as the system voltage rises from Vss toward Vcc, and the low level value of /RESET is converted into a high level signal by the inverter 11. Therefore, the NMOS transistor 12 is turned on, though the electric potential of the node N20 begins to decrease until the PMOS transistor 21 and 22 gets turned on. After /RESET goes to "high" level, NMOS transistor 12 is turned off and the reference voltage circuits 20 stars to be stabilized in its quiescent state. This is how the reference voltage maintains a predetermined value, i.e., reaches its quiescent state.
The system voltage varies. Sometimes the variation is a large drop in magnitude that is usually of relatively short duration, i.e., the system voltage can briefly drop far below Vcc. Such a drop in the system voltage can cause transistor 22 to turn off, which causes Vref to discharge from its quiescent value down to Vss.
Once Vref drops significantly below its quiescent value, very little current flows through from the voltage Vcc to ground through transistor 22 and transistor 25. Hence, Vref cannot return to its quiescent value unless /RESET undergoes a negative pulse. This can only occur, however, if the system power is removed and reapplied so as to trigger a power-on initialization. Thus, the conventional start-up circuit 10 is unable to restart the reference voltage circuit 20 if there is a dip in the system voltage sufficient to discharge Vref to Vss.